Self-modifying code

[Tim Olson]

In article <1087 at ficc.UUCP> peter at ficc.UUCP (Peter da Silva) writes:
| I have a question:
| 
| 	Why are an Icache plus a Dcache better than just
| 	a big shared cache as big as both?

When the processor has separate instruction and data buses, so
concurrent accesses can occur to both caches.

-- 
	-- Tim Olson
	Advanced Micro Devices
	(tim at delirun.amd.com)