SCSI Adapter Hardware Design
Michael Thompson
miket at bnrmtv.UUCP
Sat Apr 15 07:45:24 AEST 1989
Greetings fellow Unix PCers,
After reading various responses to my SCSI postings and talking with
a few people over the phone, I have come up with three basic variations
on the design of the SCSI adapter. The general ideas are each shown below
in a form which I hope is easily understandable. I feel each is valid
from a hardware standpoint, but the actual implementation of each varies
in complexity. Following each diagram is a short listing of what I feel
are the Pros and Cons for each design. Please let me know what you think.
*** DESIGN #1 ***
16K Static RAM Buffer with Single Chip CPU Control of SCSI Chip
TB = Tristate Bi-Directional Buffer (74LS245s)
--+
| +--+ +--+ Address +------+
| | | Address Bus | | Bus | |
|----------->|TB|---+-------------+--------------|TB|<--+----->| SCSI |--\
| Address | | | | | | | | Chip | >
U | Bus +--+ | +------+ | +------+ +--+ | +-->| |--/
N | | | 8K | | | 8K | | | | |
I | +-->| SRAM | +-->| SRAM | | | +------+
X | | | | | | |
| +-->| Lo | +-->| Hi | | | +------+
P | | | Byte | | | Byte | | | | |
C | | +------+ | +------+ +--|---|Single|
| +--+ | | +--+ | | Chip |
B |<---D0-D7-->| |<--+--------------------------->| | | | CPU |
U | |TB| | |TB|<-----+-->| |
S |<--D8-D15-->| |<----------------+------------->| | Data Bus | |
| +--+ 8 Bit Data Busses +--+ +------+
| 16 Bit
| Data Bus
--+
Pros: 1 Easiest to implement in hardware.
2 Low chip count.
3 Unix device driver easy to code.
4 Buffer contention handled in Unix device driver and firmware.
5 Don't have to worry to much about timing of Unix PC bus.
Cons: 1 Difficult to debug firmware on single chip CPU.
2 68010 must transfer data to buffer (slow and CPU overhead).
3 Hard to update firmware in single chip CPU. Must be burned in.
4 SCSI chip may not be able to transfer at max. rate.
*** DESIGN #2 ***
16K Static RAM Buffer with DMA Control of SCSI Chip During Data Xfer
TB = Tristate Bi-Directional Buffer (74LS245s)
--+
| +--+
| | | Address Bus
|----------->|TB|------------+---+-------------+-------------+
| Address | | | | | |
U | Bus +--+ | | +------+ | +------+ | +------+
N | +------+ | | | 8K | | | 8K | | | |
I | | DMA |--+ +-->| SRAM | +-->| SRAM | +-->| SCSI |--\
X | | Chip | | | | | | Chip | >
| +-------------->| | +-->| Lo | +-->| Hi | +-->| |--/
P | | | 6844 | | | Byte | | | Byte | | | |
C | | +------+ | +------+ | +------+ | +------+
| | +--+ | | +--+ |
B |<-+-D0-D7-->| |<---------------+------------------>| | |
U | |TB| | |TB|<---+
S |<--D8-D15-->| |<-----------------------------+---->| |
| +--+ 8 Bit Data Bus's +--+
| 16 Bit
| Data Bus
--+
Pros: 1 Moderate difficulty to implement in hardware.
2 SCSI chip can transfer at max. rate.
3 No firmware.
4 Buffer contention handled in hardware.
5 DMA transfer independent of Unix PC bus.
Cons: 1 68010 must transfer data to buffer (slow and CPU overhead).
2 Device driver will be complex to write.
3 Moderate amount of glue logic to contol Tri-State Buffers.
*** DESIGN #3 ***
DMA Control of SCSI Chip During Data Xfer
TB = Tristate Bi-Directional Buffer (74LS245s)
--+
| +--+
| | | Address Bus
|--+------------>|TB|---------------------------+
| | Address | | |
U | | Bus +--+ +------+ | +------+
N | | | | +-->| |
I | +--------------------->| DMA | | SCSI |---\ SCSI
X | | Chip | | Chip | >
| +-------------------->| | | |---/ LAND
P | | +------------------>|68450 | +-->| |
C | | | | | | +------+
| | | +--+ +------+ |
B |<--+----D0-D7-->| | |
U | | |TB|<--------------------------+
S |<----+-D8-D15-->| |
| +--+ 8 Bit
| 16 Bit Data Bus
| Data Bus
--+
Pros: 1 SCSI chip can transfer at max. rate.
2 No firmware.
3 Buffer contention handled in hardware.
4 Probably most elegant solution.
5 Buffer does not have to first be loaded with data.
Cons: 1 Device driver will be complex to write.
2 Lots of glue logic to contol Tri-State Buffers.
3 DMA must meet stringent Unix PC bus timing specs.
4 Overall design is hard because it must work intimately with
the Unix PC hardware.
One problem each design must overcome is the problem of attaching an
8 bit device to the Unix PCs 16 data bus. This can be solved by
use of tristate buffers to select the lower and upper byte in the data
word seperately. Where an SRAM buffer is used, each half of the word
goes to a seperate SRAM chip and in Design #3, one word will be requested
from every two bytes requested by the SCSI chip. The logic which
performs this function is not shown in the diagrams.
Surely these three designs are not the only solutions, but I am pretty
sure that the final design will closely resemble one of them. If anyone
sees a major or even minor problem in one of the designs, please let me
know. Obviously the figures up above cannot convey the level to which I
have thought each out, but I don't want to overlook something.
I also am still waiting to get a hold of the Unix PC bus specs (they should
be on their way) so some of the designs may have to be altered. We shall
see.
I plan on attending next weeks AT&T Users Group meeting in Sunnyvale so
I hope to get good feedback from people there. Hope to see you there.
Mike Thompson
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