SLC 16-bit bus ? : Summary.

[devil at TECHUNIX.BITNET]

Thanks to all the people who replied to my question, which was :

Is the Sparcstation SLC based on a 16 bit memory bus?

The reason for the question was my hearing that the SLC uses 4Mbit chips
in their SIMMS, which would give them 16x1bitx4M for 8 Mbytes...

To summarize the responses :

The SLC uses a *** 32 *** bit bus with 64KB of cache. It uses 4Mbit SIMMS,
but the chips are 1Mx4bits instead of 4Mx1bit as I assumed. This would
mean that each SIMM would give you 4MBytes in a 1Mx32bits data
configuration...  (actually 1Mx36bits, including parity).

Now for the next question : This is not the 4Mb SIMM configuration that is
most popular out there, right? Does anyone know of any third party vendors
supplying SIMM that would work on the SLC ? If so, what do they cost?

Thanks to the follwoing people who replied :

Eduardo Krell                   AT&T Bell Laboratories, Murray Hill, NJ
david at Eng.Sun.COM
schorr at ead.dsa.com (Andrew J. Schorr)
kessler at suneast.East.Sun.COM (Tom Kessler)

Gil Tene                      "Some days it just doesn't pay     |
devil at techunix.technion.ac.il   to go to sleep in the morning."  |