ATI SVGA driver for SCO-ODT?
Brian Chapman
chapman at sco.COM
Tue Jul 24 05:52:13 AEST 1990
jshekhel at feds19.prime.com (Jerry Shekhel ) writes:
>Hello. Sorry if this has been asked before, but is there a way
>to use the high-resolution modes of the ATI VGA Wonder graphics
>card with SCO Open Desktop/X/Motif? There are no ATI entries in the
>'custom' video configuration form. Please respond via follow-up,
>as I've been having problems with e-mail. Thanks to all who
>respond.
>-- Jerry Shekhel
Install this file with the path /usr/lib/grafinfo/ati/wonder.xgi
/*
* @(#) wonder.xgi 22.1 90/03/14
*
* Copyright (C) The Santa Cruz Operation, 1989.
* This Module contains Proprietary Information of
* The Santa Cruz Operation, and should be treated as Confidential.
*/
/* *********************************************************************** *
* ATI/WONDER.XGI - XEGIA(tm) GrafInfo File for ATI VGA Wonder *
* *
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
* *
* ATI.WONDER.VGA.640x350-16 *
* ATI.WONDER.VGA.640x480-16 *
* ATI.WONDER.ATIVGA.800x600-16 Super VGA 800x600 16-color *
* ATI.WONDER.ATIVGA.800x600-16-R1 Super VGA 800x600 16-color *
* *
* *********************************************************************** */
VENDOR ATI "ATI"
MODEL WONDER "VGA WONDER"
CLASS VGA "VGA"
MODE 640x350-16 "640x350 16-color" /* VGA 640x350 16 color */
MEMORY(0xA0000,0x10000); /* Base Address, Length */
PORT(0x3C2,0x3CA,0x3CC,0x3DA) /* General/External registers */
PORT(0x3C0,0x3C1); /* Attribute */
PORT(0x3C4,0x3C5); /* Sequencer */
PORT(0x3CE,0x3CF); /* Graphics */
PORT(0x3D4,0x3D5); /* CRTC */
PROCEDURE InitGraphics
{
DEVCLASS = 19;
DEVTYPE = 01;
DEVTECH = 02; /* VGA */
PIXBYTES = 80;
PIXWIDTH = 640;
PIXHEIGHT = 350;
PIXRESX = 68;
PIXRESY = 50;
PIXBITS = 1;
PIXPLANES = 4;
MAPFLAGS = 0;
BASEADDRESS = 0xA0000;
INTERLEAVE = 1;
INTERSIZE = 80;
}
PROCEDURE SetGraphics
{
in(r63,0x3DA); /* reset attr F/F */
out(0x3C0,0); /* disable palette */
r0 = 1; r1 = 1; r2 = 0x0F; r3 = 0; r4 = 6;
bout(6,0x3C4,0x3C5); /* reset, sequencer regs */
out(0x3C2,0xA3); /* misc out reg */
r0=3; bout(1,0x3C4,0x3C5) /* sequencer enable */
out(0x3D4,0x11); out(0x3D5,0); /* unprotect crtc regs 0-7 */
r0 = 0x5F; r1 = 0x4F; r2 = 0x50; r3 = 0x82; /* crtc */
r4 = 0x54; r5 = 0x80; r6 = 0xBF; r7 = 0x1F;
r8 = 0x00; r9 = 0x40; r10 = 0x00; r11 = 0x00;
r12 = 0x00; r13 = 0x00; r14 = 0x00; r15 = 0x00;
r16 = 0x83; r17 = 0x85; r18 = 0x5D; r19 = 0x28;
r20 = 0x0F; r21 = 0x63; r22 = 0xBA; r23 = 0xE3;
r24 = 0xFF; bout(25,0x3D4,0x3D5);
out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
r0 = 0x00; r1 = 0x00; r2 = 0x00; r3 = 0x00;
r4 = 0x00; r5 = 0x00; r6 = 0x05; r7 = 0x0F;
r8 = 0xFF; bout( 9, 0x3CE, 0x3CF )
in(r63,0x3DA); /* reset attr F/F */
r0 = 0x00; r1 = 0x01; r2 = 0x02; r3 = 0x03; /* palette */
r4 = 0x04; r5 = 0x05; r6 = 0x14; r7 = 0x07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
r16 = 0x01; r17 = 0x00; r18 = 0x0F; r19 = 0x00; /* attr cntlr */
bout(20,0x3C0,0x3C0)
out(0x3C0,0x20); /* enable palette */
}
PROCEDURE SetText
{
in(r63,0x3DA); /* reset attr F/F */
out(0x3C0,0); /* disable palette */
r0 = 0x01; r1 = 0x00; r2 = 0x03; r3 = 0x00; r4 = 0x02;
bout( 5, 0x3C4, 0x3C5 ) /* sequencer regs */
out(0x3C2,0x67); /* misc out reg */
r0=0x03; bout(1,0x3C4,0x3C5); /* sequencer enable */
out(0x3D4,0x11); out(0x3D5,0); /* unprotect crtc regs 0-7 */
r0 = 0x5F; r1 = 0x4F; r2 = 0x50; r3 = 0x82; /* crtc */
r4 = 0x55; r5 = 0x81; r6 = 0xBF; r7 = 0x1F;
r8 = 0x00; r9 = 0x4F; r10 = 0x0D; r11 = 0x0E;
r12 = 0x00; r13 = 0x00; r14 = 0x00; r15 = 0x00;
r16 = 0x9C; r17 = 0x8E; r18 = 0x8F; r19 = 0x28;
r20 = 0x1F; r21 = 0x96; r22 = 0xB9; r23 = 0xA3;
r24 = 0xFF; bout(25,0x3D4,0x3D5);
out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
r0 = 0x00; r1 = 0x00; r2 = 0x00; r3 = 0x00;
r4 = 0x00; r5 = 0x10; r6 = 0x0E; r7 = 0x00;
r8 = 0xFF; bout(9,0x3CE,0x3CF);
in(r63,0x3DA); /* reset attr F/F */
r0 = 0x00; r1 = 0x01; r2 = 0x02; r3 = 0x03; /* palette */
r4 = 0x04; r5 = 0x05; r6 = 0x14; r7 = 0x07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
r16 = 0x0C; r17 = 0x00; r18 = 0x0F; r19 = 0x08; /* attr cntlr */
bout(20,0x3C0,0x3C0);
out(0x3C0,0x20); /* enable palette */
}
/* ********************************************************************* */
VENDOR ATI "ATI"
MODEL WONDER "VGA WONDER"
CLASS VGA "VGA"
MODE 640x480-16 "640x480 16-color" /* VGA 640x480 16 color */
MEMORY(0xA0000,0x10000); /* Basee Address, Length */
PORT(0x3C2,0x3CA,0x3CC,0x3DA); /* General/External registers */
PORT(0x3C0,0x3C1); /* Attribute */
PORT(0x3C4,0x3C5); /* Sequencer */
PORT(0x3CE,0x3CF); /* Graphics */
PORT(0x3D4,0x3D5); /* CRTC */
PROCEDURE InitGraphics
{
DEVCLASS = 75;
DEVTYPE = 01;
DEVTECH = 02; /* VGA */
PIXBYTES = 80;
PIXWIDTH = 640;
PIXHEIGHT = 480;
PIXRESX = 68;
PIXRESY = 68;
PIXBITS = 1;
PIXPLANES = 4;
MAPFLAGS = 0;
BASEADDRESS = 0xA0000;
INTERLEAVE = 1;
INTERSIZE = 80;
}
PROCEDURE SetGraphics
{
in(r63,0x3DA); /* reset attr F/F */
out(0x3C0,0); /* disable palette */
r0 = 1; r1 = 1; r2 = 0x0F; r3 = 0; r4 = 6;
bout(5,0x3C4,0x3C5); /* reset, sequencer regs */
out(0x3C2,0xE3); /* misc out reg */
r0=3; bout(1,0x3C4,0x3C5); /* sequencer enable */
out(0x3D4,0x11); out(0x3D5,0); /* unprotect crtc regs 0-7 */
r0 = 0x5F; r1 = 0x4F; r2 = 0x50; r3 = 0x82; /* crtc */
r4 = 0x54; r5 = 0x80; r6 = 0x0B; r7 = 0x3E;
r8 = 0x00; r9 = 0x40; r10 = 0x00; r11 = 0x00;
r12 = 0x00; r13 = 0x00; r14 = 0x00; r15 = 0x00;
r16 = 0xEA; r17 = 0x8C; r18 = 0xDF; r19 = 0x28;
r20 = 0x00; r21 = 0xE7; r22 = 0x04; r23 = 0xE3;
r24 = 0xFF; bout(25,0x3D4,0x3D5);
out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
r0 = 0x00; r1 = 0x00; r2 = 0x00; r3 = 0x00;
r4 = 0x00; r5 = 0x00; r6 = 0x05; r7 = 0x0F;
r8 = 0xFF; bout(9,0x3CE,0x3CF);
in(r63,0x3DA); /* reset attribute flip/flop */
r0 = 0x00; r1 = 0x01; r2 = 0x02; r3 = 0x03; /* palette */
r4 = 0x04; r5 = 0x05; r6 = 0x14; r7 = 0x07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
r16 = 0x01; r17 = 0x00; r18 = 0x0F; r19 = 0x00; /* attr cntlr */
bout(20,0x3C0,0x3C0);
out(0x3C0,0x20); /* enable palette */
}
PROCEDURE SetText
{
in(r63,0x3DA); /* reset attr F/F */
out(0x3C0,0); /* disable palette */
r0 = 0x01; r1 = 0x00; r2 = 0x03; r3 = 0x00; r4 = 0x02;
bout( 5, 0x3C4, 0x3C5 ) /* sequencer regs */
out(0x3C2,0x67); /* misc out reg */
r0=0x03; bout(1,0x3C4,0x3C5); /* sequencer enable */
out(0x3D4,0x11); out(0x3D5,0); /* unprotect crtc regs 0-7 */
r0 = 0x5F; r1 = 0x4F; r2 = 0x50; r3 = 0x82; /* crtc */
r4 = 0x55; r5 = 0x81; r6 = 0xBF; r7 = 0x1F;
r8 = 0x00; r9 = 0x4F; r10 = 0x0D; r11 = 0x0E;
r12 = 0x00; r13 = 0x00; r14 = 0x00; r15 = 0x00;
r16 = 0x9C; r17 = 0x8E; r18 = 0x8F; r19 = 0x28;
r20 = 0x1F; r21 = 0x96; r22 = 0xB9; r23 = 0xA3;
r24 = 0xFF; bout(25,0x3D4,0x3D5);
out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
r0 = 0x00; r1 = 0x00; r2 = 0x00; r3 = 0x00;
r4 = 0x00; r5 = 0x10; r6 = 0x0E; r7 = 0x00;
r8 = 0xFF; bout(9,0x3CE,0x3CF);
in(r63,0x3DA); /* reset attr F/F */
r0 = 0x00; r1 = 0x01; r2 = 0x02; r3 = 0x03; /* palette */
r4 = 0x04; r5 = 0x05; r6 = 0x14; r7 = 0x07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
r16 = 0x0C; r17 = 0x00; r18 = 0x0F; r19 = 0x08; /* attr cntlr */
bout(20,0x3C0,0x3C0);
out(0x3C0,0x20); /* enable palette */
}
/*
* NOTE!! This entry is for an ATI VGA Wonder with a
* rev 2 chip set. The chip set revision level can be determined by
* examining the byte at offset 0x43 in the VGA BIOS (usually at
* address C000:0043) using DOS debug. This location contains the
* ATI chip set revision level as an ASCII digit - ie 0x32 for rev 2.
*/
/* ********************************************************************* */
VENDOR ATI "ATI"
MODEL WONDER "VGA WONDER"
CLASS ATIVGA "ATI VGA"
MODE 800x600-16 "800x600 16 color"
MEMORY(0xA0000,0x10000); /* Base Address, Length */
PORT(0x1CE,0x1CF); /* ATI extended register */
PORT(0x3C2,0x3CA,0x3CC,0x3DA); /* General/External registers */
PORT(0x3C0,0x3C1); /* Attribute */
PORT(0x3C4,0x3C5); /* Sequencer */
PORT(0x3CE,0x3CF); /* Graphics */
PORT(0x3D4,0x3D5); /* CRTC */
PROCEDURE InitGraphics
{
DEVCLASS = 99;
DEVTYPE = 01;
DEVTECH = 02; /* VGA */
PIXBYTES = 100;
PIXWIDTH = 800;
PIXHEIGHT = 600;
PIXRESX = 64;
PIXRESY = 54;
PIXBITS = 1;
PIXPLANES = 4;
MAPFLAGS = 0;
BASEADDRESS = 0xA0000;
INTERLEAVE = 1;
INTERSIZE = 80;
PROCEDURE SetGraphics /* ATI mode 0x54 */
{
/* set ATI extended registers to initial state */
/* ATI Reg 0 = XX00000X */
out(0x1CE, 0xB0); in(r63, 0x1CF); and(r63, 0xC1);
out(0x1CE, 0xB0); out(0x1CF, r63);
/* ATI Reg 1 = X0000XXX */
out(0x1CE, 0xB1); in(r63, 0x1CF); and(r63, 0x87);
out(0x1CE, 0xB1); out(0x1CF, r63);
/* ATI Reg 3 = XXX1XXXX */
out(0x1CE, 0xB3); in(r63, 0x1CF); or(r63, 0x10);
out(0x1CE, 0xB3); out(0x1CF, r63);
/* ATI Reg 5 = 0XXXXXXX */
out(0x1CE, 0xB5); in(r63, 0x1CF); and(r63, 0x7f);
out(0x1CE, 0xB5); out(0x1CF, r63);
/* ATI Reg 6 = XXX00XXX */
out(0x1CE, 0xB6); in(r63, 0x1CF); and(r63, 0xe7);
out(0x1CE, 0xB6); out(0x1CF, r63);
/* ATI Reg 8 = 01XXXXXX */
out(0x1CE, 0xB8); in(r63, 0x1CF); and(r63, 0x7f); or(r63, 0x40);
out(0x1CE, 0xB8); out(0x1CF, r63);
/* ATI Reg E = XXXXXX0X */
out(0x1CE, 0xBE); in(r63, 0x1CF); and(r63, 0xFD);
out(0x1CE, 0xBE); out(0x1CF, r63);
/* sequencer */
r0 = 0x1; /* reset */
r1 = 0x1;
r2 = 0xF;
r3 = 0x0;
r4 = 0x86;
bout(5, 0x3C4, 0x3C5);
/* select 36MHz clock */
/* ATI Reg E = XXX1XXXX */
out(0x1CE, 0xBE); in(r63, 0x1CF); or(r63, 0x10);
out(0x1CE, 0xBE); out(0x1CF, r63);
/* misc output reg */
out(0x3C2,0xEF);
/* remove sequencer reset */
r0 = 0x3;
bout(1,0x3C4,0x3C5);
/* unprotect crtc regs 0-7 */
out(0x3D4, 0x11); out(0x3D5, 0x0E);
/* crtc */
r0 = 0x7A; r1 = 0x63; r2 = 0x65; r3 = 0x9D;
r4 = 0x67; r5 = 0x92; r6 = 0x38; r7 = 0x1F;
r8 = 0; r9 = 0; r10 = 0; r11 = 0;
r12 = 0; r13 = 0; r14 = 0; r15 = 0;
r16 = 0x2D; r17 = 0x8E; r18 = 0x2B; r19 = 0x32;
r20 = 0xF; r21 = 0x32; r22 = 0x34; r23 = 0xE7;
r24 = 0xFF;
bout( 25, 0x3d4, 0x3D5 );
/* attribute controller */
in(r63,0x3DA); /* reset f/f */
/* palette */
r0 = 00; r1 = 01; r2 = 02; r3 = 03;
r4 = 04; r5 = 05; r6 = 0x14; r7 = 07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
/* attribute controller */
r16 = 01; r17 = 00; r18 = 0x0F; r19 = 00;
r20 = 0;
bout( 21, 0x3C0, 0x3C0 );
/* enable palette */
out( 0x3C0, 0x20);
/* graphics controller */
r0 = 0x0;
r1 = 0x0;
r2 = 0x0;
r3 = 0x0;
r4 = 0x0;
r5 = 0x0;
r6 = 0x5;
r7 = 0xF;
r8 = 0xFF;
bout( 9, 0x3CE, 0x3CF );
/* set ATI extended registers to final state for mode 0x54 */
/* ATI Reg 3 = XXX1XXXX */
out(0x1CE, 0xB3); in(r63, 0x1CF); or(r63, 0x10);
out(0x1CE, 0xB3); out(0x1CF, r63);
/* ATI Reg 8 = 00XXXXXX */
out(0x1CE, 0xB8); in(r63, 0x1CF); and(r63, 0x3F);
out(0x1CE, 0xB8); out(0x1CF, r63);
}
PROCEDURE SetText
{
/* set ATI extended registers to initial state */
/* ATI Reg 0 = XX00000X */
out(0x1CE, 0xB0); in(r63, 0x1CF); and(r63, 0xC1);
out(0x1CE, 0xB0); out(0x1CF, r63);
/* ATI Reg 1 = X0000XXX */
out(0x1CE, 0xB1); in(r63, 0x1CF); and(r63, 0x87);
out(0x1CE, 0xB1); out(0x1CF, r63);
/* ATI Reg 3 = XXX1XXXX */
out(0x1CE, 0xB3); in(r63, 0x1CF); or(r63, 0x10);
out(0x1CE, 0xB3); out(0x1CF, r63);
/* ATI Reg 5 = 0XXXXXXX */
out(0x1CE, 0xB5); in(r63, 0x1CF); and(r63, 0x7f);
out(0x1CE, 0xB5); out(0x1CF, r63);
/* ATI Reg 6 = XXX00XXX */
out(0x1CE, 0xB6); in(r63, 0x1CF); and(r63, 0xe7);
out(0x1CE, 0xB6); out(0x1CF, r63);
/* ATI Reg 8 = 01XXXXXX */
out(0x1CE, 0xB8); in(r63, 0x1CF); and(r63, 0x7f); or(r63, 0x40);
out(0x1CE, 0xB8); out(0x1CF, r63);
/* ATI Reg E = XXXXXX0X */
out(0x1CE, 0xBE); in(r63, 0x1CF); and(r63, 0xFD);
out(0x1CE, 0xBE); out(0x1CF, r63);
r0 = 0x01; r1 = 0x00; r2 = 0x03; r3 = 0x00; r4 = 0x02;
bout( 5, 0x3C4, 0x3C5 ) /* sequencer regs */
out(0x3C2,0x67); /* misc out reg */
r0=0x03; bout(1,0x3C4,0x3C5); /* sequencer enable */
/* unprotect crtc regs 0-7 */
out(0x3D4, 0x11); out(0x3D5, 0x0E);
r0 = 0x5F; r1 = 0x4F; r2 = 0x50; r3 = 0x82; /* crtc */
r4 = 0x55; r5 = 0x81; r6 = 0xBF; r7 = 0x1F;
r8 = 0x00; r9 = 0x4F; r10 = 0x0D; r11 = 0x0E;
r12 = 0x00; r13 = 0x00; r14 = 0x00; r15 = 0x00;
r16 = 0x9C; r17 = 0x8E; r18 = 0x8F; r19 = 0x28;
r20 = 0x0F; r21 = 0x96; r22 = 0xB9; r23 = 0xA3;
r24 = 0xFF; bout(25,0x3D4,0x3D5);
in(r63,0x3DA); /* reset attr F/F */
r0 = 0x00; r1 = 0x01; r2 = 0x02; r3 = 0x03; /* palette */
r4 = 0x04; r5 = 0x05; r6 = 0x14; r7 = 0x07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
r16 = 0x0C; r17 = 0x00; r18 = 0x0F; r19 = 0x08; /* attr cntlr */
bout(20,0x3C0,0x3C0);
out(0x3C0,0x20); /* enable palette */
out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
r0 = 0x00; r1 = 0x00; r2 = 0x00; r3 = 0x00;
r4 = 0x00; r5 = 0x10; r6 = 0x0E; r7 = 0x00;
r8 = 0xFF; bout(9,0x3CE,0x3CF);
}
/*
* NOTE!! This entry is for an ATI VGA Wonder with a
* rev 1 chip set. The chip set revision level can be determined by
* examining the byte at offset 0x43 in the VGA BIOS (usually at
* address C000:0043) using DOS debug. This location contains the
* ATI chip set revision level as an ASCII digit - ie 0x31 for rev 1.
*/
/* ********************************************************************* */
VENDOR ATI "ATI"
MODEL WONDER "VGA WONDER"
CLASS ATIVGA "ATI VGA"
MODE 800x600-16-R1 "800x600 16 color Revision 1"
MEMORY(0xA0000,0x10000); /* Base Address, Length */
PORT(0x1CE,0x1CF); /* ATI extended register */
PORT(0x3C2,0x3CA,0x3CC,0x3DA); /* General/External registers */
PORT(0x3C0,0x3C1); /* Attribute */
PORT(0x3C4,0x3C5); /* Sequencer */
PORT(0x3CE,0x3CF); /* Graphics */
PORT(0x3D4,0x3D5); /* CRTC */
PROCEDURE InitGraphics
{
DEVCLASS = 99;
DEVTYPE = 01;
DEVTECH = 02; /* VGA */
PIXBYTES = 100;
PIXWIDTH = 800;
PIXHEIGHT = 600;
PIXRESX = 64;
PIXRESY = 54;
PIXBITS = 1;
PIXPLANES = 4;
MAPFLAGS = 0;
BASEADDRESS = 0xA0000;
INTERLEAVE = 1;
INTERSIZE = 80;
PROCEDURE SetGraphics /* ATI mode 0x54 */
{
/* set ATI extended registers to initial state */
/* ATI Reg 0 = XX00000X */
out(0x1CE, 0xB0); in(r63, 0x1CF); and(r63, 0xC1);
out(0x1CE, 0xB0); out(0x1CF, r63);
/* ATI Reg 1 = X0000XXX */
out(0x1CE, 0xB1); in(r63, 0x1CF); and(r63, 0x87);
out(0x1CE, 0xB1); out(0x1CF, r63);
/* ATI Reg 2 = XXXXXXX0 */
out(0x1CE, 0xB2); in(r63, 0x1CF); and(r63, 0xFE);
out(0x1CE, 0xB2); out(0x1CF, r63);
/* ATI Reg 5 = 0XXXXXXX */
out(0x1CE, 0xB5); in(r63, 0x1CF); and(r63, 0x7f);
out(0x1CE, 0xB5); out(0x1CF, r63);
/* ATI Reg 6 = XXX00XXX */
out(0x1CE, 0xB6); in(r63, 0x1CF); and(r63, 0xe7);
out(0x1CE, 0xB6); out(0x1CF, r63);
/* ATI Reg 8 = 01XXXXXX */
out(0x1CE, 0xB8); in(r63, 0x1CF); and(r63, 0x7f); or(r63, 0x40);
out(0x1CE, 0xB8); out(0x1CF, r63);
/* sequencer */
r0 = 0x1; /* reset */
r1 = 0x1;
r2 = 0xF;
r3 = 0x0;
r4 = 0x86;
bout(5, 0x3C4, 0x3C5);
/* select 36MHz clock */
/* ATI Reg 2 = X1XXXXXX */
out(0x1CE, 0xB2); in(r63, 0x1CF); or(r63, 0x40);
out(0x1CE, 0xB2); out(0x1CF, r63);
/* misc output reg */
out(0x3C2,0xEF);
/* remove sequencer reset */
r0 = 0x3;
bout(1,0x3C4,0x3C5);
/* unprotect crtc regs 0-7 */
out(0x3D4, 0x11); out(0x3D5, 0x0E);
/* crtc */
r0 = 0x7A; r1 = 0x63; r2 = 0x65; r3 = 0x9D;
r4 = 0x67; r5 = 0x92; r6 = 0x38; r7 = 0x1F;
r8 = 0; r9 = 0; r10 = 0; r11 = 0;
r12 = 0; r13 = 0; r14 = 0; r15 = 0;
r16 = 0x2D; r17 = 0x8E; r18 = 0x2B; r19 = 0x32;
r20 = 0xF; r21 = 0x32; r22 = 0x34; r23 = 0xE7;
r24 = 0xFF;
bout( 25, 0x3d4, 0x3D5 );
/* attribute controller */
in(r63,0x3DA); /* reset f/f */
/* palette */
r0 = 00; r1 = 01; r2 = 02; r3 = 03;
r4 = 04; r5 = 05; r6 = 0x14; r7 = 07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
/* attribute controller */
r16 = 01; r17 = 00; r18 = 0x0F; r19 = 00;
r20 = 0;
bout( 21, 0x3C0, 0x3C0 );
/* enable palette */
out( 0x3C0, 0x20);
/* graphics controller */
r0 = 0x0;
r1 = 0x0;
r2 = 0x0;
r3 = 0x0;
r4 = 0x0;
r5 = 0x0;
r6 = 0x5;
r7 = 0xF;
r8 = 0xFF;
bout( 9, 0x3CE, 0x3CF );
/* set ATI extended registers to final state for mode 0x54 */
/* ATI Reg 0 = XXXX1XXX */
out(0x1CE, 0xB0); in(r63, 0x1CF); or(r63, 0x08);
out(0x1CE, 0xB0); out(0x1CF, r63);
/* ATI Reg 8 = 00XXXXXX */
out(0x1CE, 0xB8); in(r63, 0x1CF); and(r63, 0x3F);
out(0x1CE, 0xB8); out(0x1CF, r63);
}
PROCEDURE SetText
{
/* set ATI extended registers to initial state */
/* ATI Reg 0 = XX00000X */
out(0x1CE, 0xB0); in(r63, 0x1CF); and(r63, 0xC1);
out(0x1CE, 0xB0); out(0x1CF, r63);
/* ATI Reg 1 = X0000XXX */
out(0x1CE, 0xB1); in(r63, 0x1CF); and(r63, 0x87);
out(0x1CE, 0xB1); out(0x1CF, r63);
/* ATI Reg 3 = XXXXXXX0 */
out(0x1CE, 0xB2); in(r63, 0x1CF); and(r63, 0xFE);
out(0x1CE, 0xB2); out(0x1CF, r63);
/* ATI Reg 5 = 0XXXXXXX */
out(0x1CE, 0xB5); in(r63, 0x1CF); and(r63, 0x7f);
out(0x1CE, 0xB5); out(0x1CF, r63);
/* ATI Reg 6 = XXX00XXX */
out(0x1CE, 0xB6); in(r63, 0x1CF); and(r63, 0xe7);
out(0x1CE, 0xB6); out(0x1CF, r63);
/* ATI Reg 8 = 01XXXXXX */
out(0x1CE, 0xB8); in(r63, 0x1CF); and(r63, 0x7f); or(r63, 0x40);
out(0x1CE, 0xB8); out(0x1CF, r63);
r0 = 0x01; r1 = 0x00; r2 = 0x03; r3 = 0x00; r4 = 0x02;
bout( 5, 0x3C4, 0x3C5 ) /* sequencer regs */
out(0x3C2,0x67); /* misc out reg */
r0=0x03; bout(1,0x3C4,0x3C5); /* sequencer enable */
/* unprotect crtc regs 0-7 */
out(0x3D4, 0x11); out(0x3D5, 0x0E);
r0 = 0x5F; r1 = 0x4F; r2 = 0x50; r3 = 0x82; /* crtc */
r4 = 0x55; r5 = 0x81; r6 = 0xBF; r7 = 0x1F;
r8 = 0x00; r9 = 0x4F; r10 = 0x0D; r11 = 0x0E;
r12 = 0x00; r13 = 0x00; r14 = 0x00; r15 = 0x00;
r16 = 0x9C; r17 = 0x8E; r18 = 0x8F; r19 = 0x28;
r20 = 0x0F; r21 = 0x96; r22 = 0xB9; r23 = 0xA3;
r24 = 0xFF; bout(25,0x3D4,0x3D5);
in(r63,0x3DA); /* reset attr F/F */
r0 = 0x00; r1 = 0x01; r2 = 0x02; r3 = 0x03; /* palette */
r4 = 0x04; r5 = 0x05; r6 = 0x14; r7 = 0x07;
r8 = 0x38; r9 = 0x39; r10 = 0x3A; r11 = 0x3B;
r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
r16 = 0x0C; r17 = 0x00; r18 = 0x0F; r19 = 0x08; /* attr cntlr */
bout(20,0x3C0,0x3C0);
out(0x3C0,0x20); /* enable palette */
out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
r0 = 0x00; r1 = 0x00; r2 = 0x00; r3 = 0x00;
r4 = 0x00; r5 = 0x10; r6 = 0x0E; r7 = 0x00;
r8 = 0xFF; bout(9,0x3CE,0x3CF);
}
/* End of File - ATI-WONDER.XGI */
--
Brian Chapman uunet!sco!chapman
Pay no attention to the man behind the curtain!
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