Cache controllers, can Xenix use them?

Steve Dyer dyer at spdcc.COM
Mon Mar 6 16:21:05 AEST 1989


In article <195 at icc.UUCP> wdm at icc.UUCP (Bill Mulert) writes:
>There are now a number of high performance 80386 motherboards in
>use in personal computers. Some of these machines have the Intel
>cache controller chip, and 32 to 64k of 30ns ram. Cacheing software
>for MsDos is available for those users. 

So-called "cacheing software" under DOS is usually (not always) referring
to "DOS hard disk cacheing software".  This is not relevant to the memory
cache controller (a piece of hardware) nor is it useful or relevant
when UNIX or any OS other than DOS is running.

>My question is, is this cache controller usaeble by any of the
>Unix - Xenix kernels? Does'nt the kernel have to know about it
>in order to use it?

OK.  That would almost always be a BIOS issue, really.  A reasonable
machine powers up cache enabled, with some keyboard strokes to manipulate
cache on/off or and perhaps the speed of the machine.   Once XENIX or
UNIX is running, it needn't touch this (and once it's running you can't
use the BIOS keystroke method of manipulating it because the BIOS isn't
used after booting under UNIX.)  So, if you can force the cache on from
the keyboard, you should then be able to boot UNIX or XENIX with no special
support in the kernel.

Now... the Intel Inboard 386/AT is a 386 card for the PC AT which powers up in
"8mhz cache on" when you really want "16mhz cache on".  It comes with
DOS software to manipulate the 4 possible combinations.  But, XENIX 386
has a special boot keyword which diddles the right IO ports to get
the desired behavior.  Even in its absence, it's simple to manipulate
/dev/port in an /etc/rc startup script to get the right behavior.
It could be that other motherboards behave in a similar fashion.
You'd need to read the technical manual for the motherboard (provided
it came with one--good luck!)

-- 
Steve Dyer
dyer at ursa-major.spdcc.com aka {ima,harvard,rayssd,linus,m2c}!spdcc!dyer
dyer at arktouros.mit.edu



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