RISC (Reduced Instruction-Set Chip) vs. CISC

[Wes Peters]

In article <72969 at eerie.acsu.Buffalo.EDU>, jones at acsu.buffalo.edu (terry a jones) writes:
> 	One thing to keep in mind also, is the fact that RISC compiled objects
> are generally larger than their CISC counterparts would be.  Makes good sense
> to me, since there are fewer instructions for the compiler implementer to
> use, his code sequences will generally require more of them.  I don't have
> any hard figures available at the moment.  I'm sure that I could come up
> with some if the need arose.  I recall figures of approx. 30% in some of the
> recent literature that I have read.

There are some other tradeoffs than just instruction set size.  On the MIPS
(Stanford) chip, the compiler often packs NOPs of various sizes immediately
following multiple-cycle instructions to keep the instruction pipeline from
"stalling."  I found on the SGI Iris 4D/70 that if you optimize for minimum
space, the executables would shrink as much as 30 - 40%, but would run MUCH
(i.e. 2x to 3x) slower.  (Using SGI/MIPS f77).

One thing they never tell you when you look at a RISC system is that you
need to buy much larger disks and more memory, because code space is so
large in RISC executables.  Once again, more mips = more $$$$.  Ah well.

68040 lives!  Moto forever!

	Wes Peters
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