Information on SPARC assembly (atomic Test and Set)

[William Davidsen]

In article <5742 at lynx.UUCP> m5 at lynx.UUCP (Mike McNally) writes:

| I think that the x86 (x>0) series locks the bus on all XCHG instructions.
| The original chips required a LOCK prefix.  I don't know whether or not
| the LOCK is honored with other read/write instructions.

  Specified to lock the bus until the next instruction is complete. This
is a reasonable way to allow multiple processors to use any appropriate
interlock. I don't really like the ADDC for flag testing, since some
logic paths may require a loop until free (for short term resources) and
something could overflow.

  Why was this posted to wizards instead of arch????
	bill davidsen		(davidsen at crdos1.crd.GE.COM)
  {uunet | philabs}!crdgw1!crdos1!davidsen
"Stupidity, like virtue, is its own reward" -me