Make and Dependant/Command inferences

[John M Sellens]

Make behaves in a way that *I* sure didn't expect.  Technically,
it's probably not a bug, but I think it's kind of weird.

If the file b.c exists, the Makefile
	b.o: a.c
		echo Hello

is interpreted the same as
	b.o: a.c b.c # !!!
		echo Hello

and, if there were no commands specified (i.e. no "echo Hello"), as
	b.o: a.c b.c
		cc $(CFLAGS) -c b.c

I had always assumed that make would only try to make inferences about the
dependents of a file (in this case 'b.o') if it was not defined on the
left side of a line with a colon.  And that if I specifically define a
file dependency with no commands, that make wouldn't make some up for me.

John