Wait states, why only 4M, 68012, LEDs ; HwNote15
John B. Milton
jbm at uncle.UUCP
Tue Nov 28 16:59:29 AEST 1989
"Does expansion memory run slower than motherboard memory?"
Earlier I said that external memory has an extra wait state, making it slower
than internal memory. I was mearly repeating what someone else had told me.
After some research, I find that it is not a yes/no answer, that is, some
machine do and some don't. On page 2-23 of the Reference manual, at the top,
and on 2-26 (same text), there is a statement "19F, acting as a MUX, is set up
to select the A inputs because we are not in expansion memory...". According to
the schematics (both versions), the select pin, pin 1 is grounded and the B
inputs are NC. Hmm one says waits, one say no wait states.
I have examined 3 different motherboard vintages and found:
1. That very old motherboards (with the piggy-back board instead of custom
chips) do have a 74258 at 19F, and have patch wires on the B inputs, with
pin 1 (A/B select) not grounded. It appears to implement expansion memory
wait states.
2. Semi-old motherboards (most of the 1M) have a 74258 at 19F, with the select
pin grounded, and no patch wires on the B inputs. In this case, it appears
that expansion memory wait states have not been enabled.
3. Very new motherboards (mostly 2M 3b1) do not even have a 74258 at 19F. The
expansion memory wait state circuit was designed out.
My guess at all this is that the DMA prototype (piggy-back board) was not
quiet fast enough to access expansion memory with no wait states. To get
around this, they designed in the 74258 to add a wait state to expansion
memory accesses. Machines went out with the piggy-back board and the
74258 patched for expanion wait states. Later, when the custom chips were
ready, a lot of machines went out with the 74258 just taking up power and time.
When the motherboard layout was re-done, the 74258 was dropped.
What all this means is that, if you have an old machine with the piggy-back
board and expansion memory, you can get a performance increase by switching
to a newer motherboard. Well, I think that horse is dead.
---
"Well, if the UNIXpc only has 4M for RAM and the 68010 can
address 16M, where did the other 12M go and why can't we use it?"
What follows is a brief description of where things are in the UNIXpc address
space. This should give you an idea of how sloppy the decoding is. Sloppy
decoding is not as bad as it might seem, as it's easier to implement and
faster. In the address below, "x" means "don't care" or any value. All the
addresses are in hex, so each "x" is 16. Multiply the "x"s together to get
the size of the space each I/O register or device takes up. For descriptions
of the bits in the I/O registers, see the appropriate /usr/include/sys/*.h
files. The notation [1236-8] means 1, 2, 3, 6, 7, 8. For example,
"xx[ef][7f]xxx[13-f]" would expand to the BIT pattern:
"xxxx xxxx 111x x111 xxxx xxxx xxxx 111x"
UNIXpc memory map:
The UNIXpc memory is divided into 4 major 4 megabyte chunks:
I xx000000 to xx3fffff RAM memory, fast cycle access (400ns)
II xx400000 to xx7fffff fast cycle I/O
III xx800000 to xxbfffff slow cycle read (appears to also be writable)
IV xxc00000 to xxffffff slow cycle I/O
I
xx000000 to xx1fffff Internal mappable RAM (400ns cycle)
xx200000 to xx3fffff External mappable RAM (400ns cycle (or slower))
II
xx[4-7]0x[08]00 to xx40x[7f]ff Map RAM, 2k
xx[4-7]1xxxx General Status Register
xx[4-7]20000 to xx427fff Video RAM, 32k (31320 on screen)
xx[4-7]3xxxx Bus Status Register 0
xx[4-7]4xxxx Bus Status Register 1
xx[4-7]5xxxx Phone status
xx[4-7]6xxxx DMA count register
xx[4-7]7xxxx Line printer status register
xx[4-7]8xxxx Real Time Clock
xx[4-7]9[08]xxx Handset relay
xx[4-7]9[19]xxx Line select 2
xx[4-7]9[2a]xxx Hook relay 1
xx[4-7]9[3b]xxx Hook relay 2
xx[4-7]9[4c]xxx Line 1 hold
xx[4-7]9[5d]xxx Line 2 hold
xx[4-7]9[6e]xxx Line 1 A-lead
xx[4-7]9[7f]xxx Line 2 A-lead
xx[4-7]axxxx Miscellaneous Control Register
xx[4-7]bxxxx TM/DIALWR
xx[4-7]cxxxx CSR
xx[4-7]dxxxx DMA, Address register
xx[4-7]exxxx Disk Control Register
xx[4-7]fxxxx Line printer data register
II
xx800000 to xxbfffff Boot ROM, temporarily located at xx000000 during RESET
III
xxc00000 Expansion slot 0 I/O
xxc40000 Expansion slot 1 I/O
xxc80000 Expansion slot 2 I/O
xxcc0000 Expansion slot 3 I/O
xxd00000 Expansion slot 4 I/O
xxd40000 Expansion slot 5 I/O
xxd80000 Expansion slot 6 I/O
xxdc0000 Expansion slot 7 I/O
xx[ef][08]xxx0 WD1010 Data register
xx[ef][08]xxx2 WD1010 Error register
xx[ef][08]xxx4 WD1010 Count register
xx[ef][08]xxx6 WD1010 Sector number register
xx[ef][08]xxx8 WD1010 Cylinder number low register
xx[ef][08]xxxa WD1010 Cylinder number high register
xx[ef][08]xxxc WD1010 Sector drive head register
xx[ef][08]xxxe WD1010 Status/Command register
xx[ef][08]xxxf (ignored)
xx[ef][19]xxx0 WD2797 Status/Command register
xx[ef][19]xxx2 WD2797 Track register
xx[ef][19]xxx4 WD2797 Sector register
xx[ef][19]xxx6 WD2797 Data register
xx[ef][19]xxx[13578-f] (unused)
xx[ef][2a]xxxx Miscellaneous Control Register 2 (used with P5.1)
xx[ef][3b]xxxx Real Time Clock data bits
General Control Register
xx[ef][4c][08]xxx EE
xx[ef][4c][19]xxx P1E
xx[ef][4c][2a]xxx BP
xx[ef][4c][3b]xxx ROMLMAP
xx[ef][4c][4c]xxx L1 MODEM
xx[ef][4c][5d]xxx L2 MODEM
xx[ef][4c][6e]xxx D/N CONNECT
xx[ef][4c][7f]xxx Whole screen reverse video
xx[ef][5d]xxx0 8274, Ch A data
xx[ef][5d]xxx2 8274, Ch B data
xx[ef][5d]xxx4 8274, Ch A status/command
xx[ef][5d]xxx6 8274, Ch B status/command
xx[ef][5d]xxx[1357-f] (unused)
xx[ef][6e]0xxx Line control
xx[ef][6e]3xxx Relay and lamp drivers
xx[ef][6e]4xxx Options A/S and handshake
xx[ef][6e]5xxx Options CCITT and disconnect
xx[ef][6e]6xxx RD, SD and chip test
xx[ef][6e]8xxx Transceiver control 1
xx[ef][6e]9xxx Transceiver control 2
xx[ef][6e]axxx Transceiver status
xx[ef][6e][b-f]xxx (undefined)
xx[ef][7f]xxx0 6850 (keyboard) Status register
xx[ef][7f]xxx2 6850 (keyboard) Data register
xx[ef][7f]xxx[13-f] (unused)
Note that every "xxx" above is 4k, and every "xxxx" is 64k of address space.
There are some very interesting things to note here. One very interesting thing
is that the 16k of boot ROM takes up an entire 4M chunk! Note that this is up
in the slow cycle half of memory (1000ns), and is not refreshed. There does
not seem to be circuitry to restrict writes to this area. This area could be
replaced with a ROM-disk, with the boot ROM in the first partition. Since
EPROM devices are faster now than when the UNIXpc was designed, the slow cycle
access could be defeated. Note that all of the I/O in the second 4M chunk
(xx400000 to xx7fffff) could fit in xx400000 to xx4fffff if A20 and A21 were
used. This would free up 3M of fast cycle space.
--
"I've heard of the 68000, 68008, 68010, 68020, 68030, and the
68040, but what is the 68012?"
Well, this one got me thinking the other night. What, you've never heard of
the 68012? If you've got the data sheet for the 68010, it's right there on
the cover: "MC68010/MC68012 16-/32-Bit Virtual Memory Microprocessors". The
68012 is EXACTLY the same as the 68010 from a software point of view. The only
difference between the 68012 and the 68010 is that the 68012 has 8 additional
pins: A24, A25, A26, A27, A28, A29, A31 and RMC. That's right A30 *IS NOT*
provided. This allows the 68012 to access 2G of memory, in two separate 1G
areas from 00000000 to 3fffffff (same as 40000000 to 7fffffff) and
from 80000000 to dfffffff (same as c0000000 to ffffffff). The 68012 is
only available in an 84 pin grid array package. The RMC pin is the same as the
68020 pin by the same name, and is asserted during Read-Modify-Write bus
cycles, like those produced by the TAS instruction. Word has it that chip in
the 68012 is exactly the same as the 68010, it just has more wires bonded to
the die. Word also has it that the chip was specially produced for one customer.
Why they couldn't run out A30 when they added so many GND pins is beyond me.
All this is fine and wonderful, but there are problems. Memory above the 16M
boundry would have to be limited to supervisor mode (kernel space), since there
is no MMU access. Exceptions would be applications like the "vidpal". If the
upper byte of any of the address registers used by the kernel is EVER set to
non-zero, then this approach will be tougher to use. Since the UNIXpc mother-
board and expansion bus don't support the additional address lines, the only
place to use them would be on a daughter board.
--
"When the system won't boot, don't the LEDs on the side indicate
the problem?"
When the machine is first started, the boot ROM goes though some tests before
it tries to boot. If one of these tests fails, the machine halts with the
number of the test on the LEDs. The LEDs are behind the gates on the left side
of the machine, near the front.
LED 1 Red
LED 2 Green
LED 3 Yellow
LED 4 Red (I guess they ran out of colors)
Test 4 3 2 1 Problem
1 off off off on Failed telephone initialization
2 off off on off Failed video RAM test
3 off off on on Failed map RAM test
4 off on off off Failed to set map RAM to unity map
5 off on off on Failed dynamic RAM test
6 off on on off Failed initialization
7 off on on on Failed to find loader on disk
I guess I should have put this in HwNote01.
John
--
John Bly Milton IV, jbm at uncle.UUCP, n8emr!uncle!jbm at osu-cis.cis.ohio-state.edu
(614) h:252-8544, w:469-1990; N8KSN, AMPR: 44.70.0.52; Don't FLAME, inform!
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