IOCC Performance/Programming Questions

[Mike Massa]

I'm writing device drivers for some MCA cards with 8-bit register ports. I'm
trying to achieve as high a data transfer rate as possible. The best I've
been able to do so far is 2.5 MB/s with an assembly language routine that 
loads 16 general purpose registers from memory and then stores them to the 
card's single 8-bit register via the IOCC using the load/store multiple 
instructions (code at end of post). The cards are currently wired to decode 
a 64-byte wide address space for one 8-bit register so all data is only 
written to one register.

I put a scope on the iowrite line of the card and noted the following:
    - each 1-byte transfer from the IOCC to the device register requires
      2 bus cylces (200 ns)
    - the IOCC misses 1 bus cycle between each 1 byte transfer - total xfer 
      time is therefore 3 bus cycles (300 ns)
    - there is a 2 microsecond delay between 64-byte (16 word) bursts on the
      MCA. This seems to be the IOCC synching with the CPU and executing
      the transfer loop.
    
I assume that the IOCC is missing a cycle because it is performing dynamic
bus sizing to accomodate the 8-bit card. I was able to get back-to-back
32-bit transfers using a true 32-bit card. 

Questions:

- is there any way to achieve back-to-back 8-bit transfers from the IOCC?
- can multiple transfers be made to a single io address - ie can I prevent
  the IOCC from incrementing the address ptr between words/bytes
- can the 2 microsecond delay between bursts be decreased?
- is there a better way to do this?

Thanks,

Mike Massa
Distributed Systems Laboratory
University of Pennsylvania
massa at aurora.cis.upenn.edu

------------------------------------------------------------------------------

###################
# Transfer code
##################

# buf_p = pointer to data to write
# ioreg_p = pointer to device register
# blkcnt = number of 16 word (64 byte) blocks to write

	mtctr	blkcnt			# load blkcnt into counter register
	b	test			# jump to loop test
loop:     				# write 16-word blocks out	
	lm	16,0(buf_p)		# read  block from buf in memory
	stm	16,0(ioreg_p)		# write block to device register
	ai	buf_p,buf_p,64		# increment buffer src address
test:
	bdn	loop			# decrement blkcnt & jump if not zero